The invention relates to the field of fabricating integrated capacitors. In particular it relates to structure of, and methods for fabrication of, integrated capacitors as used in ferroelectric memory integrated circuits. The invention relates in particular to deposition, masking, and etching, of the dielectric and electrode layers of ferroelectric capacitors in ferroelectric memory integrated circuits.
Standard Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) devices are considered volatile memory devices because data stored therein is lost when power is lost. Nonvolatile memory devices are those that can retain data despite loss of power.
At present, there is a strong market for EEPROM (Electrically Erasable, Programmable Read Only Memory), and Flash EEPROM nonvolatile memory devices. These devices tend to be slow to write, often having write times on the order of milliseconds, while read times range generally between one nanosecond and one microsecond. The great difference between read and write times, together with the block-erase character of Flash EEPROM, complicates design of some systems. CMOS SRAM or DRAM with battery backup power for data retention can provide symmetrical, fast, read and write times in nonvolatile memory but is expensive, requires presence of a battery, and limits system life or requires eventual battery replacement.
It is known that Ferroelectric Random Access Memory (FRAM) is a nonvolatile memory technology having potential for both read and write times below one microsecond. FRAM nonvolatile memory devices based on Lead Zirconium Titanate (PZT) ferroelectric storage capacitors as memory elements integrated with CMOS addressing, selection, and control logic are known in the art and are commercially available. PLZT is a Lanthanum-doped form of PZT wherein some of the lead is replaced with Lanthanum, for purposes of this patent the term PZT includes PLZT. It is known that PZT may additionally be doped with strontium and calcium to improve its ferroelectric dielectric properties. Ferroelectric storage capacitors having a strontium bismuth tantalate (SBT) dielectric are also known in the art. For purposes of this patent the term Ferroelectric Dielectric includes both PZT and SBT materials.
It is expected that FRAM devices having smaller device geometries and smaller ferroelectric storage capacitors than currently available devices will offer greater speed and storage density at lower cost. Producing such FRAM devices requires production of well-defined, uniform, high quality, ferroelectric storage capacitors integrated with CMOS addressing and control logic.
Ferroelectric storage capacitors of FRAM devices have a bottom electrode interfacing with a ferroelectric layer, often PZT or SBT, that serves as the ferroelectric dielectric. The ferroelectric layer is typically deposited on top of the bottom electrode, and a top electrode is deposited on top of the ferroelectric layer. These layers are masked and etched to define the size and location of each capacitor. A passivation layer is formed over the resulting capacitors. This layer is masked and etched to allow connection of each capacitor to other components of each memory cell and to other components, such as CMOS addressing, selection, and control logic of the integrated circuit.
A prior process for fabricating an array of ferroelectric storage capacitors is described in U.S. Pat. No. 6,090,443, (the ""443 patent) entitled xe2x80x9cMulti-Layer approach for optimizing Ferroelectric Film Performancexe2x80x9d and assigned to Ramtron International Corporation, Colorado Springs, Colo., the disclosure of which is incorporated herein by reference. This process involves the following steps all performed after deposition of an adhesion layer onto a substrate, the substrate may be a partially processed CMOS integrated circuit wafer:
Deposition of a metallic bottom electrode layer.
Deposition of a PZT layer.
Annealing the deposited PZT.
Depositing a top electrode layer.
Once these layers are deposited, they must be patterned to form an array through at least one masking and etching sequence. Each masking and etching sequence requires deposition of a photoresist over the array of partially processed capacitors, aligning the array with a photomask, exposing, developing, and curing the photoresist, and etching to remove undesired portions of the layers. The etching is controlled by remaining cured photoresist. Etching is typically performed with dry etch techniques, such as plasma etching or ion milling.
It is known that typical dry etch techniques as commonly used in processing capacitor arrays cause damage to the cured photoresist used to control etching. This damage may result in undercutting at edges of resist opening. As cured photoresist layers are eaten away, this damage may also result in undesired etching of those portions of the layers that should remain to form the array.
Typically, fabricating such a capacitor array is performed through a sequence of two or more masking and etching sequences because excessive damage to the photoresist occurs before the undesired portions of the layers are adequately removed. It is known, however, that repeated masking and etching sequences are expensive and can result in undesirable edge profiles of remaining portions as a result of misalignment. The undesirable edge profiles may necessitate greater spacing between capacitor array elements than may be otherwise possible. In particular, it is repeated photomasking operations that drive up cost.
It is also known that exposure of photoresist to dry etch causes release of an assortment of chemical compounds that contain carbon and hydrogen. It is also known that excessive exposure of ferroelectric dielectrics, such as PZT, to these compounds, including hydrogen, can induce undesirable properties in the dielectrics. For this patent, induction of undesirable properties by these compounds is known as photoresist byproduct poisoning of the dielectric. It is therefore desirable to protect the dielectric layer from these chemical compounds during the etching process.
A hardmask is a layer of resistant material that is patterned with photolithographic techniques as known in the art and used to control circuit processing. The resistant material is a material that is more stable than cured photoresist under at least some conditions, these conditions may include etching, diffusing, or oxidizing conditions. Hardmask layers are occasionally used in the processing of integrated circuits; although they are typically formed of nonconductive material. For example, standard CMOS processing uses a nonconductive silicon nitride hardmask layer to protect future diffused areas during field oxidation. U.S. Pat. No. 5,936,306 describes a process utilizing a titanium silicide layer as a conductive hard mask for controlling wet etch of titanium nitride. U.S. Pat. No. 5,998,258 discloses a process for forming capacitors having a barium strontium titanate dielectric wherein a hardmask layer of titanium or tantalum nitride is used to pattern a top electrode. U.S. Pat. No. 5,998,258 also suggests, in column 4, using a hardmask layer in fabrication of capacitors having PZT ferroelectric dielectric and metallic top electrode.
Strontium ruthenium oxide, SrRuO3 (SRO) is known to be a conductive metal oxide that has interesting magnetic properties. J. C. Jiang, X. Q. Pan and C. L. Chen discuss deposition of SRO films by laser ablation in an article entitled: xe2x80x9cMicrostructure of Epitaxial SrRuO3 Thin Films on (001) SrTiO3xe2x80x9d.
This process involves the following steps all performed after deposition of an adhesion layer onto a substrate, the substrate may be a partially processed CMOS integrated circuit wafer:
Deposition of a metallic bottom electrode layer.
Deposition of a PZT dielectric layer.
Annealing the deposited dielectric.
Depositing a top electrode layer.
Depositing a strontium ruthenium oxide (SRO) hardmask layer over the top electrode layer.
Depositing, exposing, developing, and curing a photoresist layer over the SRO layer.
Dry etching of the SRO and top electrode layers, while destroying the photoresist layer.
Dry etching of the dielectric as defined by openings etched in the SRO and top electrode layers.
Depositing of a passivation and/or encapsulation layer.
Once these steps are performed, processing of the ferroelectric memory integrated circuit and its capacitor array continues as known in the art. Further processing includes: masking and etching of undesired bottom electrode portions, masking and etching of vias in the passivation layer to allow contact to electrodes of the capacitors array, as well as deposition, masking, and etching of circuit metalization and insulator layers.
The great advantage of the process is that depositing, masking, exposing, and curing of only one photoresist layer is required to define areas of the top electrode and ferroelectric dielectric layers.
A secondary advantage of the present process is that photoresist byproduct poisoning of the dielectric is prevented because the photoresist layer is removed before the PZT dielectric is exposed to etching plasma.
Since the process of the present invention can result in removal of the photoresist layer before the dielectric is exposed, less photoresist byproduct poisoning occurs than with standard processing. Further, it becomes possible to define the top electrode and ferroelectric dielectric layers of the capacitor array with a single masking and etching sequence, thereby reducing costs.
The foregoing and other features, utilities and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings.